1. Field of the Invention
The present invention relates to growth of semiconductor materials, and, more particularly, to heteroepitaxial growth such as gallium arsenide on silicon.
2. Description of the Related Art
Recently, many researchers have investigated growth of semiconductor-device quality gallium arsenide (GaAs) on silicon wafers and fabrication of active devices in the GaAs. Such devices would combine the higher mobility of carriers in GaAs with the greater mechanical strength and thermal conductivity of a silicon substrate. For example, R. Fishcer et al. GaAs/AlGaAs Heterojunction Bipolar Transistors on Si Substrates. 1985 IEDM Tech. Digest 332, report GaAs/AlGaAs heterojunction bipolar transistors grown on silicon substrates and having current gains of .beta.=13 for a 0.2 .mu.m thick base. Similarly, G. Turner et al, Picosecond Photodetector Fabricated in GaAs Layers Grown on Silicon and Silicon On Sapphire Substrates, 1985 IEDM Tech. Digest 468, report response times of 60 picoseconds for photoconductive detectors fabricated in GaAs on silicon. These articles also note that majority carrier devices such as MESFETs fabricated in GaAs on silicon have performance approaching that of homoepitaxial devices: and this has encouraged efforts to integrate GaAs/AlGaAs optoelectronic and high-frequency devices and silicon devices on the same wafer to utilize high-data-rate optical interconnections to reduce the number of wire interconnections. Selective recrystallization of amorphous GaAs can use the high resistivity of noncrystalline GaAs; see, for example, A. Christou et al, Formation of (100) GaAs on (100) silicon by Laser Recrystallization, 48 Appl. Phys. Lett. 1516 (1986). However, defects in GaAs grown on silicon substrates remain a problem.
Various methods have been used to limit defects in GaAs grown on silicon, and these include deposition of prelayers of As or Ga, AlAs/GaAs superlattices for growth initiation, silicon-germanium transition layers, and various strained layer superlattices (InGaAs/GaAs for example) as buffer layers for the purpose of filtering out threading dislocations. But such methods have drawbacks including unexpected misfit dislocation and thermal cracks at strained interfaces during epitaxial growth or later high temperature processing steps. Further, these methods are not simple.